This invention relates to integrated circuits, and in particular, to static random access memory (SRAM) circuits. This invention also relates to methods and circuits for storing data in SRAM circuits.
There are two general types of memory circuits: “volatile” and “nonvolatile”. Volatile memory loses its stored information when power is removed from the circuit whereas nonvolatile memory retains its stored information even when power is disconnected from the circuit. Within the “volatile” memory category, there are also two main types: “static” random access memory (or SRAM) and “dynamic” random access memory (or DRAM). Once data is written into an SRAM memory cell it remains available for reading as long as power is supplied to the circuitry. Conversely, a DRAM memory cell requires constant refreshing in order for its data to remain available for reading. If a refresh cycle does not occur within a certain period of time, the data is lost and cannot be recovered.
Examples of publications describing SRAM cells include:    1. Jianping Hu et al., “A Novel Low-Power Adiabatic SRAM with an Energy-Efficient Line Driver,” International Conference on Communications, Circuits and Systems, June 2004, p. 1151 (hereafter “Publication 1)”.    2. Joohee Kim et al., “Energy Recovering Static Memory,” International Symposium on Low Power Electronics and Design, August 2002, p. 92.    3. Jianping Hu et al., “Low Power Dual Transmission Gate Adiabatic Logic Circuits and Design of SRAM,” Midwestern Symposium on Circuits and Systems, 2004, p. 1-565.    4. Nestoras Tzartzanis et al., “Energy Recovery for the Design of High-Speed, Low-Power Static RAMs,” International Symposium on Low Power Electronics and Design, 1996.    5. Joohee Kim et al., PCT Patent Application WO 03/088459, entitled “Low-Power Driver with Energy Recovery”, Oct. 23, 2003.
It is common for computer integrated circuit chips (or ICs) to have SRAM embedded within them in order to store data locally and make that data available for processing at some future time. This embedded memory operates significantly faster than “off chip” external memory when communicating with the processor. Some computer chips (typically called microprocessor units or MPUs) only have embedded memory (both volatile and nonvolatile). Many of these MPU chips are used in battery-powered mobile, wearable or surgically-implantable applications where power consumption must be minimized for cost and/or performance reasons.
FIG. 1 shows a common architecture for an SRAM cell 1 whereby two inverters INV1, INV2 are connected in a feedback loop which allows 360 degrees of phase inversion. 360 degrees of phase inversion is also called “positive feedback” and creates a regenerative effect whereby cell 1 is stable in a state that has the positive supply rail voltage of the inverters on one of the internal nodes X, Xn and the negative supply rail voltage on the other internal node Xn, X. For example, assuming both switches S0 and S1 are open, if node X is at a logical 1 then node Xn is at a logical 0. If both nodes X, Xn are driven to a logical 1 simultaneously, or driven to a logical 0 simultaneously, cell 1 is unstable and will transition to a stable state whereby only one of nodes X, Xn is at a logical 1 and the other node Xn, X is at a logical 0. Cell 1 remains in this state as long as a new value is not written into cell 1 and cell 1 remains powered up to an adequate voltage level. When it is desired to store new data in SRAM cell 1, switches S0 and S1 are closed to sample bit lines BIT and BITn. As can be seen in FIG. 1, bit lines BIT and BITn are driven by tristate drivers DRV, DRVn with data signals DATA and DATAn, respectively, when a write enable signal WE is asserted.
FIG. 2 shows the transistor-level equivalent of SRAM cell 1 wherein switches S0 and S1 are implemented as NMOS transistors MN0 and MN1 and inverters INV1 and INV2 are implemented with transistors MN2, MN3, MP2 and MP3. Transistors MN0 and MN1 are controlled by a write word line WORD. When switches S0 and S1 are closed (or equivalently transistors MN0 and MN1 are on) to write data into cell 1, the output leads of inverters INV1 and INV2 are “back-driven” in order for SRAM cell 1 to switch states (assuming the new data to be stored in cell 1 is the opposite of the data previously stored in cell 1). When SRAM cell 1 is back-driven, current is consumed by inverters INV1, INV2 until they finish transitioning to the new state. FIG. 3 shows how this occurs. (The symbols for the transistors in FIG. 3 have been modified to show the on-resistances.) First, drivers DRV, DRVn drive bit lines BIT, BITn to the logical values that SRAM cell 1 will store in the next write cycle. In this case it is assumed that node X is at a logical 0 and node Xn is at a logical 1 before the write cycle. Bit lines BIT and BITn are first driven to logical 1 and 0 respectively. (A logical 1 is assumed to correspond to voltage “VDD” in this case). After the voltages on bit lines BIT, BITn have settled, word line WORD is pulsed, thereby switching on transistors MN0 and MN1. This example assumes a switch resistance of 2000 ohms when either switching transistor MN0, MN1 is in the “on” state. This example also assumes an “on” switch resistance of 10,000 ohms for transistor MN2 and 20,000 ohms for transistor MP3. (Transistors MN3 and MP2 are “off” at the beginning of the write cycle and have very large resistance values of approximately 10,000,000,000 ohms each when off.) The initial source current (I-Source) in FIG. 3 is given by:I-Source=VDD/(10K+2K)If VDD equals 1V then I-Source=83.4 uA. The sink current (I-Sink) on the opposite side of the cell will be given by:I-Sink=VDD/(20K+2K)
Again, if VDD equals 1V then I-Sink equals 45.4 uA. This example does not take into consideration the output resistance of the bit line drivers DRV, DRVn which is assumed here to be approximately zero ohms. This is a reasonable approximation given that the SRAM switch and inverter device resistances are typically much larger than the bit line driver resistance.
The I-Source and I-Sink currents cause power consumption during write operations. Such power consumption is undesirable.
Another source of power consumption lies in the fact that SRAM cells are typically arranged in arrays comprising rows and columns of cells, each column being accessed by a pair of bit lines (e.g. lines BIT, BITn in FIGS. 1 to 3). Owing to the length of the bit lines, the bit lines tend to be highly capacitive. Voltage on bit lines BIT, BITn is raised and lowered by the transistors MN5, MN6, MP5, MP6 within drivers DRV, DRVn. During the process of raising and lowering the voltage on bit lines BIT, BITn, and charging and discharging the bit line capacitance, power is consumed by transistors MN5, MN6, MP5 and MP6 as they transition from on to off or from off to on. (The capacitance associated with bit lines BIT, BITn is symbolically illustrated as capacitors C, Cn, respectively.) It would be desirable to reduce such power consumption.